The data link layer, or layer 2, is the second layer of the seven-layer OSI model of computer networking. This layer is the protocol layer that transfers data between nodes on a network segment across the physical layer.[2] The data link layer provides the functional and procedural means to transfer data between network entities and may also provide the means to detect and possibly correct errors that can occur in the physical layer.
The data link layer is concerned with local delivery of frames between nodes on the same level of the network. Data-link frames, as these protocol data units are called, do not cross the boundaries of a local area network. Inter-network routing and global addressing are higher-layer functions, allowing data-link protocols to focus on local delivery, addressing, and media arbitration. In this way, the data link layer is analogous to a neighborhood traffic cop; it endeavors to arbitrate between parties contending for access to a medium, without concern for their ultimate destination. When devices attempt to use a medium simultaneously, frame collisions occur. Data-link protocols specify how devices detect and recover from such collisions, and may provide mechanisms to reduce or prevent them.
Examples of data link protocols are Ethernet, Point-to-Point Protocol (PPP), HDLC and ADCCP. In the Internet Protocol Suite (TCP/IP), the data link layer functionality is contained within the link layer, the lowest layer of the descriptive model, which is assumed to be independent of physical infrastructure.
The data link provides for the transfer of data frames between hosts connected to the physical link. Within the semantics of the OSI network architecture, the protocols of the data link layer respond to service requests from the network layer, and perform their function by issuing service requests to the physical layer. That transfer can be reliable or unreliable; many data link protocols do not have acknowledgments of successful frame reception and acceptance, and some data link protocols might not even perform any check for transmission errors. In those cases, higher-level protocols must provide flow control, error checking, acknowledgments, and retransmission.
The frame header contains the source and destination addresses that indicate which device originated the frame and which device is expected to receive and process it. In contrast to the hierarchical and routable addresses of the network layer, layer 2 addresses are flat, meaning that no part of the address can be used to identify the logical or physical group to which the address belongs.
In some networks, such as IEEE 802 local area networks, the data link layer is described in more detail with media access control (MAC) and logical link control (LLC) sublayers; this means that the IEEE 802.2 LLC protocol can be used with all of the IEEE 802 MAC layers, such as Ethernet, Token Ring, IEEE 802.11, etc., as well as with some non-802 MAC layers such as FDDI. Other data-link-layer protocols, such as HDLC, are specified to include both sublayers, although some other protocols, such as Cisco HDLC, use HDLC's low-level framing as a MAC layer in combination with a different LLC layer. In the ITU-T G.hn standard, which provides a way to create a high-speed (up to 1 Gigabit/s) local area network using existing home wiring (power lines, phone lines and coaxial cables), the data link layer is divided into three sub-layers (application protocol convergence, logical link control and media access control).
The data link layer is often divided into two sublayers: logical link control (LLC) and media access control (MAC).[3] The uppermost sublayer, LLC, multiplexes protocols running at the top of the data link layer, and optionally provides flow control, acknowledgment, and error notification. The LLC provides addressing and control of the data link. It specifies which mechanisms are to be used for addressing stations over the transmission medium and for controlling the data exchanged between the originator and recipient machines.
MAC may refer to the sublayer that determines who is allowed to access the media at any one time (e.g. CSMA/CD). Other times it refers to a frame structure delivered based on MAC addresses inside.
There are generally two forms of media access control: distributed and centralized.[4] Both of these may be compared to communication between people. In a network made up of people speaking, i.e. a conversation, they will each pause a random amount of time and then attempt to speak again, effectively establishing a long and elaborate game of saying "no, you first".
The Media Access Control sublayer also performs frame synchronization, which determines the start and end of each frame of data in the transmission bitstream. It entails one of several methods: timing-based detection, character counting, byte stuffing, and bit stuffing.
The services provided by the data link layer are:
In addition to framing, the data link layer may also detect and recover from transmission errors. For a receiver to detect transmission errors, the sender must add redundant information as an error detection code to the frame sent. When the receiver obtains a frame it verifies whether the received error detection code matches a recomputed error detection code.
An error detection code can be defined as a function that computes the r (amount of redundant bits) corresponding to each string of N total number of bits. The simplest error detection code is the parity bit, which allows a receiver to detect transmission errors that have affected a single bit among the transmitted N + r bits. If there are multiple flipped bits then the checking method might not be able to detect this on the receiver side. More advanced methods than parity error detection do exist providing higher grades of quality and features.
A simple example of how this works using metadata is transmitting the word "HELLO", by encoding each letter as its position in the alphabet. Thus, the letter A is coded as 1, B as 2, and so on as shown in the table on the right. Adding up the resulting numbers yields 8 + 5 + 12 + 12 + 15 = 52, and 5 + 2 = 7 calculates the metadata. Finally, the "8 5 12 12 15 7" numbers sequence is transmitted, which the receiver will see on its end if there are no transmission errors. The receiver knows that the last number received is the error-detecting metadata and that all data before is the message, so the receiver can recalculate the above math and if the metadata matches it can be concluded that the data has been received error-free. Though, if the receiver sees something like a "7 5 12 12 15 7" sequence (first element altered by some error), it can run the check by calculating 7 + 5 + 12 + 12 + 15 = 51 and 5 + 1 = 6, and discard the received data as defective since 6 does not equal 7. More sophisticated error detection and correction algorithms are designed to reduce the risk that multiple transmission errors in the data would cancel each other out and go undetected. An algorithm that can even detect if the correct bytes are received but out of order is the cyclic redundancy check or CRC. This algorithm is often used in the data link layer.
In the Internet Protocol Suite (TCP/IP), OSI's data link layer functionality is contained within its lowest layer, the link layer. The TCP/IP link layer has the operating scope of the link a host is connected to, and only concerns itself with hardware issues to the point of obtaining hardware (MAC) addresses for locating hosts on the link and transmitting data frames onto the link. The link-layer functionality was described in RFC 1122 and is defined differently than the data link layer of OSI, and encompasses all methods that affect the local link. The TCP/IP model is not a top-down comprehensive design reference for networks. It was formulated for the purpose of illustrating the logical groups and scopes of functions needed in the design of the suite of internetworking protocols of TCP/IP, as needed for the operation of the Internet. In general, direct or strict comparisons of the OSI and TCP/IP models should be avoided, because the layering in TCP/IP is not a principal design criterion and in general, considered to be "harmful" (RFC 3439). In particular, TCP/IP does not dictate a strict hierarchical sequence of encapsulation requirements, as is attributed to OSI protocols.
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Page 21-Wire is a device communications bus system designed by Dallas Semiconductor Corp. that provides low-speed (16.3 kbit/s[1]) data, signaling, and power over a single conductor.
 1-Wire is similar in concept to I²C, but with lower data rates and longer range. It is typically used to communicate with small inexpensive devices such as digital thermometers and weather instruments. A network of 1-Wire devices with an associated master device is called a MicroLAN. The protocol is also used in small electronic keys known as a Dallas key or iButton. One distinctive feature of the bus is the possibility of using only two wires — data and ground. To accomplish this, 1-Wire devices include an 800 pF capacitor to store charge and power the device during periods when the data line is active. 1-Wire devices are available in different packages: integrated circuits, a TO-92-style transistor, and a portable form called an iButton or Dallas key which is a small stainless-steel package that resembles a watch battery. Manufacturers also produce devices more complex than a single component that use the 1-Wire bus to communicate. 1-Wire devices can fit in different places in a system. It might be one of many components on a circuit board within a product. It also might be a single component within a device such as a temperature probe. It could be attached to a device being monitored. Some laboratory systems connect to 1-Wire devices using cables with modular connectors or CAT-5 cable. In such systems, RJ11 (6P2C or 6P4C modular plugs, commonly used for telephones) are popular. Systems of sensors and actuators can be built by wiring together many 1-Wire components. Each 1-Wire component contains all of the logic needed to operate on the 1-Wire bus. Examples include temperature loggers, timers, voltage and current sensors, battery monitors, and memory. These can be connected to a PC using a bus converter. USB, RS-232 serial, and parallel port interfaces are popular solutions for connecting a MicroLan to the host PC. 1-Wire devices can also be interfaced directly to microcontrollers from various vendors. iButtons are connected to 1-Wire bus systems by means of sockets with contacts that touch the "lid" and "base" of the canister. Alternatively, the connection can be semi-permanent with a socket into which the iButton clips, but from which it is easily removed. Each 1-Wire chip has a unique identifier code. This feature makes the chips, especially iButtons, suitable electronic keys. Some uses include locks, burglar alarms, computer systems, manufacturer-approved accessories and time clocks. iButtons have been used as Akbil smart tickets for the public transport in Istanbul. Power suppliesApple MagSafe and MagSafe 2 connector-equipped power supplies, displays, and Mac laptops use the 1-Wire protocol to send and receive data to and from the connected Mac laptop, via the middle pin of the connector. Data include power supply model, wattage, and serial number; and laptop commands to send full power, and illuminate the red or green light-emitting diodes in the connector.[2] Genuine Dell laptop power supplies use the 1-Wire protocol to send data via the third wire to the laptop computer about power, current and voltage ratings. The laptop will then refuse charging if the adapter does not meet requirements.[3] In any MicroLan, there is always one master in overall charge, which may be a personal computer or a microcontroller. The master initiates activity on the bus, simplifying the avoidance of collisions on the bus. Protocols are built into the master's software to detect collisions. After a collision, the master retries the required communication. A 1-Wire network is a single open drain wire with a single pull-up resistor. The pull-up resistor pulls the wire up to 3 or 5 volts. The master device and all the slaves each have a single open-drain connection to drive the wire, and a way to sense the state of the wire. Despite the "1-Wire" name, all devices must also have a second wire, a ground connection to permit a return current to flow through the data wire.[4] Communication occurs when a master or slave briefly pulls the bus low, i.e., connects the pull-up resistor to ground through its output MOSFET. The data wire is high when idle, and so it can also power a limited number of slave devices. Data rates of 16.3 kbit/s can be achieved. There is also an overdrive mode that speeds up the communication by a factor of 10. A short 1-Wire bus can be driven from a single digital I/O pin on a microcontroller. A universal asynchronous receiver-transmitter (UART) can also be used.[5] Specific 1-Wire driver and bridge chips are available. Universal Serial Bus "bridge" chips are also available. Bridge chips are particularly useful to drive cables longer than 100 m. Up to 300-meter twisted pairs, i.e., telephone cables, have been tested by the manufacturer. These extreme lengths require adjustments to the pull-up resistances from 5 to 1 kΩ. The master starts a transmission with a reset pulse, which pulls the wire to 0 volts for at least 480 μs. This resets every slave device on the bus. After that, any slave device, if present, shows that it exists with a "presence" pulse: it holds the bus low for at least 60 μs after the master releases the bus. To send a binary number "1", the bus master sends a very brief (1–15 μs) low pulse. To send a binary number "0", the master sends a 60 μs low pulse. The falling (negative) edge of the pulse is used to start a monostable multivibrator in the slave device. The multivibrator in the slave reads the data line about 30 μs after the falling edge. The slave's internal timer is an inexpensive analog timer. It has analog tolerances that affect its timing accuracy. Therefore, the pulses are calculated to be within margins. Therefore, the "0" pulses have to be 60 μs long, and the "1" pulses can't be longer than 15 μs. When receiving data, the master sends a 1–15-μs 0-volt pulse to start each bit. If the transmitting slave unit wants to send a "1", it does nothing, and the bus goes to the pulled-up voltage. If the transmitting slave wants to send a "0", it pulls the data line to ground for 60 μs. The basic sequence is a reset pulse followed by an 8-bit command, and then data are sent or received in groups of 8 bits. When a sequence of data is being transferred, errors can be detected with an 8-bit CRC (weak data protection). Many devices can share the same bus. Each device on the bus has a 64-bit serial number, of which 8 bits are used as a checksum, thus allowing a "universe" of 256 (over 7.2 × 1016) unique device identities. The least significant byte of the serial number is an 8-bit number that tells the type of the device. The most significant byte is a standard (for the 1-Wire bus) 8-bit CRC.[6] There are several standard broadcast commands, as well as commands used to address a particular device. The master can send a selection command, then the address of a particular device. The next command is executed only by the addressed device. The 1-Wire bus enumeration protocol, like other singulation protocols, is an algorithm the master uses to read the address of every device on the bus. Since the address includes the device type and a CRC, recovering the roster of addresses also produces a reliable inventory of the devices on the bus. To find the devices, the master broadcasts an enumeration command, and then an address, "listening" after each bit of an address. If a slave's address matches all the address bits sent so far, it returns a 0. The master uses this simple behavior to search systematically for valid sequences of address bits. The process is much faster than a brute force search of all possible 56-bit numbers, because as soon as an invalid bit is detected, all subsequent address bits are known to be invalid. The 56-bit address space is searched as a binary tree, allowing up to 75 devices to be found per second. The order in which device addresses are discovered by this enumeration protocol is deterministic and depends only on the device type and serial number. Bit-reversing these 56 bits yields the order of discovery for devices using Maxim's published algorithm (algorithm defined in Application Note 187[7]). The search algorithm can be implemented in an alternative form, initially searching paths with address bits equal to 1, rather than 0. In this case, inverting the 56 address bits and then reversing them yields the order of discovery. The location of devices on the bus is sometimes significant. For these situations, a microcontroller can use several pins, or the manufacturer has a 1-Wire device that can switch the bus off or pass it on. Software can therefore explore sequential bus domains.[6] The following signals were generated by an FPGA, which was the master for the communication with a DS2432 (EEPROM) chip, and measured with a logic analyzer. A logic high on the 1-Wire output, means the output of the FPGA is in tri-state mode and the 1-Wire device can pull the bus low. A low means the FPGA pulls down the bus. The 1-Wire input is the measured bus signal. On input sample time high, the FPGA samples the input for detecting the device response and receiving bits. When developing and/or troubleshooting the 1-Wire bus, examination of hardware signals can be very important. Logic analyzers and bus analyzers are tools that collect, analyze, decode, and store signals to simplify viewing the high-speed waveforms.
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What layer of the TCP IP stack is responsible for moving the packet from the source node to the final destination node?
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